Port/Constraint "Cheat Sheet"
For the BurchED BED-SPARTAN2+ FPGA Design/Eval Kit.BurchEd FPGA Plug-On Board notes. Generally I connect the plug-on boards as follows: LED-7 - J3 LED-7 - J4 (LED-8 = J4) RAM - J6, J9 SWITCHES - J8 CPU-IO - J11 Note: You *cannot* connect CPU-IO to J8 since the oscillator pins don't connect to clock inputs, further if you connect it to J10 its clock oscillator will interfere with the on-board oscillator. HEX Map for Display LED-7 BRD PIN J3 J4 J10 # | a b c d e f g --------- --- ---- ---- --- --+-------------- dp 5 P188 P162 P58 0 | 1 1 1 1 1 1 0 L a 11 P195 P168 P67 1 | 0 1 1 0 0 0 0 E b 12 P199 P172 P68 2 | 1 1 0 1 1 0 1 F c 8 P192 P165 P61 3 | 1 1 1 1 0 0 1 T d 7 P191 P164 P60 4 | 0 1 1 0 0 1 1 e 6 P189 P163 P59 5 | 1 0 1 1 0 1 1 f 10 P194 P167 P63 6 | 1 0 1 1 1 1 1 g 9 P193 P166 P62 7 | 1 1 1 0 0 0 0 8 | 1 1 1 1 1 1 1 dp 4 P187 P161 P57 9 | 1 1 1 0 0 1 1 R a 18 P205 P179 P75 A | 1 1 1 0 1 1 1 I b 19 P206 P180 P81 b | 0 0 0 1 1 1 1 G c 15 P202 P175 P71 C | 1 0 0 1 1 1 0 H d 14 P201 P174 P70 d | 0 1 1 1 1 0 1 T e 13 P200 P173 P69 E | 1 0 0 1 1 1 1 f 17 P204 P178 P74 F | 1 0 0 0 1 1 1 g 16 P203 P176 P73 * hex chars in u/l case Pin CPU-IO BRD J11 SWITCH BOARD J8 --- ------------- --------- ------------ -------- 1 5V => JP10-1 5V => JP4-1 2 OSC1 out => P80 NC => P24 3 OSC2 out => P82 NC => P27 4 MOUSE CLK => P83 S2-8 (15) => P29 5 MOUSE DTA => P84 S2-7 (14) => P30 6 CTS (IN) => P86 S2-6 (13) => P31 7 RTS (OUT) => P87 S2-5 (12) => P33 8 TxD (OUT) => P88 S2-4 (11) => P34 9 RxD (IN) => P89 S2-3 (10) => P35 10 KYBD CLK => P90 S2-2 ( 9) => P36 11 KYBD DTA => P94 S2-1 ( 8) => P37 12 VSync => P95 S1-8 ( 7) => P41 13 HSync => P96 S1-7 ( 6) => P42 14 BLU0 => P97 S1-6 ( 5) => P43 15 BLU1 => P98 S1-5 ( 4) => P44 16 GRN0 => P99 S1-4 ( 3) => P45 17 GRN1 => P100 S1-3 ( 2) => P46 18 RED0 => P101 S1-2 ( 1) => P47 19 RED1 => P102 S1-1 ( 0) => P48 20 GND => GND GND => GND P49 = TEST LED P77 = CLOCK (24Mhz by default)