VHDL Source code for GEN_S1

-- Generate Segment 1 in one gate.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity GEN_S1 is
    Port ( data : in std_logic_vector(3 downto 0);
           seg : out std_logic);
end GEN_S1;

architecture behavioral of GEN_S1 is

begin
    with data select 
	seg <= '0' when "0101",
		 '0' when "0110",
		 '0' when "1100",
		 '0' when "1111",
		 '0' when "1110", 
		 '0' when "1011",
		 '1' when others;
end behavioral;