HEX Decoder/Driver for
Seven Segment LED Displays
Design a 4-to-7 decoder circuit that converts a 4 bit value into hexadecimal digits on a 7 segment LED display. You should do two designs, in the first design use a process block and a case statement. In the second design use a concurrent assignment statement.
Pin Direction Description DATA[3..0]
These four input pins determine the value shown on the display. Use the BED-DIPSWITCH board connected to J9 and assign these to locations P102, P101, P100, and P99. (labeled 3 through 0 on the switch board) SEGS[6..0]
Connect these pins to the outer segments (labeled a-g) of a seven segment LED display. For a BED-7SEGMENT-DISPLAYS board, connect it to J4 and use locations P179, P180, P175, P174, P173, P178, and P176. TEST
This pin is used to "test" the display, when asserted true, all segments on the display should light up. Use the BED-DIPSWITCH board connected to J9 and assign this to location P29 (labeled 15 on the switch board) BLANK IN This pin is used to "blank" the display, when asserted true all segments on the display should extinguish. It should have priority over TEST above. Use the BED-DIPSWITCH board connected to J9 and assign this to location P30 (labeled 14 on the switch board.)
This project uses two ways to synthesize a 7-segment display driver out of purely combinatorial logic. While both designs work in exactly the same way, they may not be equivalent in terms to the number of gates they consume.
This is perhaps the most frustrating aspect of VHDL, trying to out guess the logic inference engine.
This project's primary goal is to use two different VHDL constructs, the case statement and the concurrent signal assignment statement, to generate a decoder. You should also examine the synthesis report and determine which one (if either) uses fewer gates. Try setting the optimization for area rather than speed and see what effect, if any, that has on the output.
The HEX Decoder/Driver circuit has three primary inputs, a TEST pin, a BLANK pin, and the DATA[3..0] pins. The output is 7 lines labeled SEGS[6..0] that are connected to the 'a-g' pins on a seven segment display.
Display drivers are a really useful circuit since one really great use of an FPGA or CPLD is to replace a bunch of logic that is driving a display panel with a single chip, further the panel can be "reconfigured" without re-wiring. This latter benefit, a natural consequence of using programmable logic, is great when prototyping. The advantages of the TEST and BLANK pins also becomes more obvious when you build these panels.
The TEST pin allows you to see if all the lights on the display panel are working, this can eliminate two questions when debugging a faulty display "Is there power?" and "Are the displays connected?" Once you know that both of these answers are YES then you can work back from the display into the circuit.
The BLANK pin is great for shutting off the display, and if you pulse it you can actually "dim" the display. See the going further section below for ways to explore this usage.
This project will be re-used as a component in later projects, thus it is good to know how it works and how big it is. Try different ways of coding it (I've done at least 6) and compare their various trade-offs. Other things to explore:
- Count up the gates in each synthesis report. How well does your tool infer different versions?
- Convert the display such that it infers a latch to hold the value even when the input data lines change.
- Which is better : A display driver that latches the output to the segments or a latch that drives the data lines? Try implementing both and look at the gate count.
- The BLANK pin over-rides both TEST and DATA. Try connecting it to a clock circuit that has a 75% duty cycle then one with a 50% duty cycle. Neat huh?
Copyright © 2001, Chuck McManis, All Rights Reserved