VHDL Source code for TBSEL

-- Test/Blank/Select
--
-- This defines a gate that implements test and blank.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TBSEL is
    Port ( TST : in std_logic;
           BLNK : in std_logic;
           DATA : in std_logic;
           Q : out std_logic);
end TBSEL;

architecture behavioral of TBSEL is

begin
    Q <= '0' when BLNK = '1'
 	  else '1' when TST = '1'
	  else DATA;
end behavioral;