# Project #1 : Clock Generator

• The Project -- This is the first project in my journey, making an LED blink.
• The Solution -- This is the code I wrote for it.

On the premise that you must crawl before you can walk, this first project was really all about learning how to use the WebPack ISE tools rather than doing any serious learning about VHDL. However, I did manage to learn something VHDLish in the process.

The 'jumpstart' project that Tony Burch includes on his web site flashes the LED with a simple counter, It also included instructions on how to get started with WebPACK ISE.  I "improved" it by making the LED flash at exactly 10hz when used with a 24Mhz crystal.

Of course the major learning experience was starting up the WebPACK tools, creating a project, synthesizing it and then using BEDLOAD to load it into the FPGA and watch the LED blink. However I also learned that BEDLOAD had a bug that caused it not to reload the "RBT" file even though you opened a "new" one, so you have to exit BEDLOAD every time.

Further, I learned that in VHDL you can only assign something once in the body of a process. Once you've done assigned something you're done. So code that makes total sense to a software type:

```	counter <= counter + 1.
if (counter > 1199999) then
counter <= 0;
end if;```

Is completely bogus VHDL! The reason is that what VHDL is "inferring" (aka guessing) is that you are latching a value of counter + 1, and then some combinatorial logic is checking to see if the bit pattern matches 1199999, Now the tricky bit comes when the comparator result is true and you are asking counter to then latch something else (in this case 0).

Unfortunately, you can't do that in real life with real latches and counters. So you get a synthesis error (but not a syntax error!) Is that weird or what?

So the correct code becomes:

```	if (counter = 199999) then
counter <= 0;
else
counter <= counter + 1;
end if;```

The difference here is that now the output of the comparison (a Boolean value) will determine if the counter latches "0" or latches "count + 1". And that you can build in hardware with a counter that muxes either 0 or counter+1 to the input pins based on the output of a comparator and then latches it on the rising edge of a clock.

This project is very simple because it doesn't need any plug-on boards. Basically you can use it to verify that you know how to type in VHDL code and download the completed result to the Spartan2 board.