VHDL Source code for HEX Display
Brute force method!!

-- A Brute Force Version of the HEX Decoder
--
-- When the tools screws up (as it did in this case) you sometimes have to tell it
-- exactly what you want. Fortunately you can do that too in VHDL. This is the equivlent
-- of the asm("...") statement in gcc. Basically you create some gate primitives and
-- use them as components wired up the way that you want them wired up. 
--
-- I resorted to this technique when the WebPACK VHDL compiler was using 25 logic elements
-- to synthesize a simple combinational circuit. This version synthesizes in only 14.
-- However it is extremely ugly. The Synopsys FPGA Express tool always synthesized in 7
-- logic elements (it knows the Xilinx architecture apparently) so I use it for my final
-- synthesis step when I'm short on gates. 
-- Other files : TBSEL, GEN_S0, GEN_S1, GEN_S2, GEN_S3, GEN_S4, GEN_S5, and GEN_S6
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity hexb_display is
    Port ( test : in std_logic;
           blank : in std_logic;
           data : in std_logic_vector(3 downto 0);
           segs : out std_logic_vector(6 downto 0));
end hexb_display;

architecture structural of hex5_display is
    component TBSEL port (TST : in std_logic; 
	 BLNK : in std_logic;
	 DATA : in std_logic;
	 Q : out std_logic);
    end component;

    component GEN_S0 port (DATA : in std_logic_vector(3 downto 0);
	  SEG : out std_logic);
    end component;

    component GEN_S1 port (DATA : in std_logic_vector(3 downto 0);
	  SEG : out std_logic);
    end component;

    component GEN_S2 port (DATA : in std_logic_vector(3 downto 0);
	  SEG : out std_logic);
    end component;

    component GEN_S3 port (DATA : in std_logic_vector(3 downto 0);
	  SEG : out std_logic);
    end component;

    component GEN_S4 port (DATA : in std_logic_vector(3 downto 0);
	  SEG : out std_logic);
    end component;

    component GEN_S5 port (DATA : in std_logic_vector(3 downto 0);
	  SEG : out std_logic);
    end component;

    component GEN_S6 port (DATA : in std_logic_vector(3 downto 0);
	  SEG : out std_logic);
    end component;

    -- End component Declarations 
    signal leds : std_logic_vector(6 downto 0);
begin
    U1: GEN_S0 port map (data => data, seg => leds(0));
    U2: GEN_S1 port map (data => data, seg => leds(1));
    U3: GEN_S2 port map (data => data, seg => leds(2));
    U4: GEN_S3 port map (data => data, seg => leds(3));
    U5: GEN_S4 port map (data => data, seg => leds(4));
    U6: GEN_S5 port map (data => data, seg => leds(5));
    U7: GEN_S6 port map (data => data, seg => leds(6));
    U8: TBSEL port map (TST => test, BLNK => blank, DATA=> leds(0), Q => segs(0));
    U9: TBSEL port map (TST => test, BLNK => blank, DATA=> leds(1), Q => segs(1));
    U10: TBSEL port map (TST => test, BLNK => blank, DATA=> leds(2), Q => segs(2));
    U11: TBSEL port map (TST => test, BLNK => blank, DATA=> leds(3), Q => segs(3));
    U12: TBSEL port map (TST => test, BLNK => blank, DATA=> leds(4), Q => segs(4));
    U13: TBSEL port map (TST => test, BLNK => blank, DATA=> leds(5), Q => segs(5));
    U14: TBSEL port map (TST => test, BLNK => blank, DATA=> leds(6), Q => segs(6));
end structural;